1. Technical Field
The present invention relates generally to a semiconductor apparatus, and more particularly, to a delay control circuit and a clock generation circuit including the same.
2. Related Art
In general, a semiconductor apparatus utilizing memory performs an operation in synchronization with a clock. In a synchronous type semiconductor apparatus, input and output data should be precisely synchronized with an external clock. The semiconductor apparatus receives the external clock, converts the external clock into an internal clock, and uses the converted internal clock. However, as the internal clock is transmitted through a clock buffer and a transmission line, a phase difference occurs between the internal clock and the external clock. In order to compensate for the phase difference, the semiconductor apparatus generally utilizes a phase-locked loop or a delay-locked loop.
The delay-locked loop may increase an effective data output period by compensating for the phase difference occurring between the internal clock and the external clock. The delay-locked loop moves the phase of the internal clock to precede the phase of the external clock by a predetermined time, such that output data may be outputted synchronized with the external clock.
FIG. 1 is a block diagram schematically showing the configuration of a conventional delay-locked loop 10. In FIG. 1, the delay-locked loop 10 includes a delay line 11, a delay modeling unit 12, a phase detection unit 13, and a delay line control unit 14. The delay line 11 receives an input clock CLKI, delays it by the value set by the delay line control unit 14, and generates a delayed clock CLKD. The delay modeling unit 12 delays the delayed clock CLKD by a modeled delay value and generates a feedback clock CLKF. The phase detection unit 13 compares the phases of the input clock CLKI and the feedback clock CLKF and generates a phase detection signal PDOUT. The delay line control unit 14 receives the phase detection signal PDOUT and generates a delay control signal UP/DN, which may newly set the delay value of the delay line 11.